comp.sys.arm

Long-form reference · 5,561 words · about a 24-minute read

Where comp.sys.arm sat

The second level of a comp.* name is the department, and comp.sys.* was the department for particular machines. Read down the Internet Systems Consortium’s newsgroups file and the pattern is unmistakable: comp.sys.amiga.* with thirteen rooms, comp.sys.atari.* with six, comp.sys.apple2.* with four, comp.sys.apollo and comp.sys.att standing alone. In each case the name after comp.sys is a manufacturer or a model line, and the traffic is whatever the owners of that hardware need to know. comp.sys.arm is the odd entry on that shelf, because ARM is not a machine. It is an instruction set, and by the time the group was created the machines implementing it were being built by companies with nothing else in common.

Its nearest neighbour was the Acorn family, which the ISC newsgroups file still lists with nine groups, one of them moderated. The descriptions are the ones the file carries today:

• comp.sys.acorn.advocacy — “Why Acorn computers and programs are better.”
• comp.sys.acorn.announce — “Announcements for Acorn and ARM users. (Moderated)”
• comp.sys.acorn.apps — “Acorn software applications.”
• comp.sys.acorn.extra-cpu — “Extra CPUs in Acorn computers.”
• comp.sys.acorn.games — “Discussion of games for Acorn machines.”
• comp.sys.acorn.hardware — “Acorn hardware.”
• comp.sys.acorn.misc — “Acorn computing in general.”
• comp.sys.acorn.networking — “Networking of Acorn computers.”
• comp.sys.acorn.programmer — “Programming of Acorn computers.”

That shape was reached over four votes in as many years. The result of a reorganisation posted on 15 July 1992 created the advocacy group (151 votes to 50), a moderated announce group (189 to 24) and a technical group (174 to 32), while a proposal to rename the parent group to comp.sys.acorn.misc failed at 138 to 57 — the reorganiser’s own summary observed that one of the contestants had been knocked out of the race. A games group followed, passing 289 to 33 in a result posted on 31 March 1994. In February 1995 a second reorganisation finished the job: the rename to comp.sys.acorn.misc finally passed, apps, hardware, networking and programmer were created, and the technical group that had been created less than three years earlier was removed. A group for processor cards, comp.sys.acorn.extra-cpu, arrived in January 1996 by 384 to 38.

The boundary between the machine groups and the architecture group was written down, twice. The charter for comp.sys.acorn.programmer, as published in the 1995 result, reads: “For discussions of Acorn related programming matters. This includes Acorn specific C, BASIC, Assembler (6502 or ARM) Generic ARM code should be discussed in comp.sys.arm.” Acorn-specific assembler here; assembler for the architecture as such, there. The extra-cpu proposal of November 1995 drew the same line from the other side: its charter covered processor cards for Acorn machines but specifically excluded “matters which *solely* related to the processor in question”. That proposal exists at all because, as its rationale explains, the Acorn and Aleph 486 second-processor cards for the Risc PC had produced “a steady and large thirst for information and problem fixes” that was being “erratically posted across one or more of the existing Acorn newsgroups”.

The other neighbour was comp.arch, whose description in the same file is two words: “Computer architecture.” That is the group for the discipline rather than for any of its products — pipelines, caches, register files, the merits of reduced instruction sets in the abstract. A processor-architecture group is a third thing again: not a machine, not the general theory, but one instruction set considered as something engineers have to build with. The 1994 proposal said as much in its rationale, observing that ARM discussion had until then appeared “in various technical newsgroups related to products that include ARM processors, or in more general newsgroups such as comp.arch”, while other discussion had “no obviously suitable newsgroup”. For the shape of the hierarchy itself, see the comp.* hierarchy page.

The vote of 1994

Unusually for a group of this size, the entire creation record survives in the news.announce.newgroups archive. The Request for Discussion was posted on 22 September 1994 by Kevin Wheatley, writing from Leeds University, with three co-proponents: Paul Hedderly at the University of York, Philip R. Banks in New Zealand, and Clive Jones at armltd.co.uk — that is, at the company whose architecture was being proposed as a subject. The status sought was unmoderated, the distribution world.

The list of groups the RFD was cross-posted to is a map of who used ARM chips in 1994: comp.sys.acorn.tech and comp.sys.acorn.announce for the British desktop constituency, comp.sys.newton.programmer and comp.sys.newton.announce for Apple’s handheld, which used the ARM610, rec.games.video.3do for the 3DO Interactive Multiplayer, built around an ARM60, and comp.arch for the architects. Brief pointers went to seven further groups: comp.sys.ti, comp.dsp, comp.lsi, comp.multimedia, comp.sys.handhelds, comp.sys.palmtops and rec.games.programmer. Three separate hardware cultures, none of which would have read the others’ groups, were being invited into one room.

comp.sys.arm will be an unmoderated forum for discussion of the ARM processor architecture, and devices that implement it, as well as support chips such as memory and video controllers. Suitable topics include programming and hardware integration techniques, software, evaluation and benchmarking, book reviews and announcements.

Various ARM-related products already have their own newsgroups. Where this is the case, discussions not of general interest to all users of the ARM processor architecture should use these other newsgroups in preference to comp.sys.arm.

The rationale attached to that charter is worth reading for what it expected the group to become. Its authors hoped that “repositories for coding examples, circuit diagrams, conference papers, etc. would accumulate”, and that announcements of general interest “could be made by Advanced RISC Machines, its semiconductor partners, and companies including ARM processors in their products”. This was a group proposed partly as a vendor channel, by a group of proponents that included an employee of the vendor, and nobody involved appears to have thought that odd.

The Call for Votes went out on 1 November 1994, taken by Ron Dippold under the banner of the Usenet Volunteer Votetakers, with the ballot closing at 23:59:59 UTC on 22 November. The result was posted on 1 December: 349 in favour, 19 against, 368 valid votes, clearing both of the standing thresholds — a two-thirds majority and a margin of at least a hundred. As the rules required, the votetaker published the full list of voters with their addresses. Of the addresses on it, roughly two hundred are British and a further forty or so are continental European, the great majority of both academic; a scattering carry armltd.co.uk and acorn.co.uk. That is a fair portrait of where the architecture’s users were before it went into telephones.

David C. Lawrence, then moderator of news.announce.newgroups, sent the newgroup control message on 7 December 1994 and repeated it on 14 December and again on 7 January 1995, the routine belt-and-braces of a network where not every server heard the first announcement. The machinery of Requests for Discussion, Calls for Votes and five-day waiting periods is set out on the soc.* hierarchy page; comp.sys.arm is a textbook run through it.

Cambridge, 1983: what paid for a processor

Acorn Computers could afford to design a processor because a schools broadcaster had made it rich. The BBC Micro, introduced in December 1981, was a conventional 6502 machine made unusually quick by fast dynamic memory, and it sold well enough that Acorn’s profits rose from £3,000 in 1979 to £8.6 million by July 1983. In September 1983 the company floated on the Unlisted Securities Market with a market capitalisation of about £135 million. The processor project started the following month.

It started because the successor machine had nowhere to go. Acorn had set itself the target of a business computer ten times the performance of the BBC Micro at the same price, and the engineers, having surveyed what the semiconductor industry was selling, concluded that the available 16-bit parts were expensive, demanded large numbers of support chips, and were barely faster than what they already had. Two things then pushed them over. One was the series of reports out of the University of California, Berkeley suggesting that a simple design could outrun a complicated one. The other was a visit by Steve Furber and Sophie Wilson to the Western Design Center in Mesa, Arizona, where they saw high-school students producing chip layouts on Apple II machines. The inference drawn was not that the students were exceptional but that the task was not sacred.

The division of labour is well attested. Wilson developed the instruction set, writing a simulation of the processor in BBC BASIC that ran on a BBC Micro with a 6502 second processor; Hermann Hauser, Acorn’s chief executive, approved the project on the strength of it and assembled a small team to design the chip itself, with Furber as a principal designer. One standard reference puts the team that produced the first ARM microprocessor between 1983 and 1985 at twelve people. Wilson, then publishing as Roger Wilson, later rewrote BBC BASIC in ARM assembly language; the resulting code was dense enough that it became the standard torture test for ARM emulators.

Acorn did not build chips, so it chose a silicon partner: VLSI Technology, already supplying it with ROMs and custom parts. Acorn provided the design; VLSI provided the layout and the production. The arrangement was kept so quiet that when Olivetti negotiated a controlling stake in Acorn in 1985 — the company having very nearly gone under that February, when a creditor issued a winding-up petition — it was not told about the development team until the negotiations had been finalised.

26 April 1985

The first ARM was fabricated on VLSI Technology’s three-micron double-level-metal CMOS process using full custom techniques. The samples were tested on 26 April 1985 and worked first time, which for a first silicon attempt by a team of that size was less a triumph than a reprieve. The part comprised 24,000 transistors, about 8,000 gates — a figure worth holding next to the Motorola 68000’s roughly 68,000, six years its senior. There was no microcode and no cache.

The clock figure needs care, because two different numbers circulate. Secondary accounts commonly say that ARM1 ran at 6 MHz. The designer’s own contemporaneous statement is that the target clock was 4 MHz and the part ran at 8, and that the ARM Evaluation System drove it at 3.3 MHz and 6.6 MHz for initial and page-mode memory cycles respectively. The 6 MHz in circulation appears to be a rounding of the machine, not the chip.

ARM1 was not sold as a computer. It went first into a second processor for the BBC Micro, where it was used to develop the simulation software that finished the rest of the chip set and to speed up the design tools for its own successor. Those support chips — VIDC, the video and sound controller; MEMC, the memory controller; and IOC, the input-output controller, the “support chips” of this group’s charter line — arrived on 22 October 1985, 25 February 1986 and 30 April 1986 respectively, and were all reported right first time as well. ARM Evaluation Systems, second processors for the BBC Micro and Master, went on sale from July 1986 under the Acorn OEM Products brand, to developers and researchers rather than to the public.

The standard reference is itself a Usenet article

The dates in the preceding section are not drawn from a company history or a museum label. They come from a posting to comp.arch made on 2 November 1988 by [email protected], under the subject “Some facts about the Acorn RISC Machine”. Wikipedia’s article on the ARM architecture cites that posting, and no other source, for the 26 April 1985 date. It is a Usenet article: written by the author of the instruction set, posted to a newsgroup, and not published anywhere else first.

Its opening explains itself with a candour that has not dated. “There have now been enough partially correct postings about the Acorn RISC Machine (ARM) to justify semi-official comment.” What follows is a technical brief of about fifteen hundred words: the four-chip set and the slogan behind it, “MIPs for the masses”; the fabrication process and the first-silicon dates; transistor counts and die sizes; the note that “every instruction is conditional” and that all instructions are abortable, to support virtual memory; the Sanyo second-source agreement of April 1988; the part numbers VLSI Technology had given the chips; the compilers, the operating systems and the ports; and a four-instruction sequence for reversing the byte order of a register, offered without comment as though everyone would obviously want one.

Two details in it are pure engineering culture. The author records that the team ran a competition to see who would use the addressing form with four genuinely different registers, and that “the graphics people won it too easily”. And on byte order: “ARM’s byte sex is as VAX and NS32000 (little endian).” The article closes on a disclaimer that the whole thing is “a fiction constructed by an outline processor, a thesaurus and a grammatical checker”. It is a document written by someone who expected to be read by peers and corrected by them, which is exactly the register a technical newsgroup produced and very little else did.

A directory of preserved newsgroups can make a modest claim on the strength of this. The earliest full public account of the architecture, the one the reference works still cite, was not a press release and not a data sheet. It was a post, in a group, answering people who had got it slightly wrong.

ARM2, the Archimedes and the desktop years

Once Acorn had decided what machine it was building, the processor was redesigned to go faster. The 1988 posting lists the changes plainly: more fast-interrupt registers, bringing the total to 27, because the real-time code would not fit in the smaller set; a multiply instruction that processed two bits per cycle and stopped when the multiplier was exhausted; a set of coprocessor interfaces; and the removal of one addressing form, register scaled by a register, on the grounds that it was too hard to compile for. The two-micron part was right first time on 19 February 1987, and the posting gives its peak as 18 MHz and its transistor count as 25,000; later secondary accounts usually round the ARM2 to 30,000.

VLSI Technology was granted a licence to sell the chips to anyone, and renamed them for its own catalogue: VL86C010 for the processor, VL86C110, VL86C310 and VL86C410 for the memory, video and input-output controllers. It also made the processor available as a cell that other designers could drop into an application-specific chip. This was not yet the licensing business that ARM Ltd would later build, but it was the same instinct — a design worth more as a part number in someone else’s catalogue than as a chip in Acorn’s own boxes. The 1988 posting relays VLSI’s own projections from a trade journal of that July: the part in 1.5 micron at an 18 to 20 MHz clock, a future shrink to one micron at “perhaps 40MHz” with the price falling from $50 to $15, and expected sales for 1988 of ninety to a hundred thousand units. Those are the numbers of a minor component vendor, not of an industry standard.

The Acorn Archimedes was launched on 6 June 1987: the A305 with half a megabyte of memory, the A310 with one, the A440 with four megabytes and a twenty-megabyte hard disc. The 1988 posting puts the range at between eight hundred and three thousand pounds with monitor and mouse; a later reference gives £799 to £2,299. It has been described as the first commercially available RISC-based microcomputer. Its operating system, Arthur, was written in machine code and filled half a megabyte of ROM; the posting’s summary of its features — windows, anti-aliased fonts and sound synthesis — reads oddly modern for 1988. Arthur was renamed RISC OS at its second release, in May 1989. Acorn also shipped a Unix, RISC iX, based on 4.3BSD.

An ARM3 followed with a 4 KB cache, sold both as standard equipment and as upgrades for existing Archimedes machines; in 1994 the Risc PC arrived with an ARM610. And then the company that had started all of it stopped. Acorn closed its workstation division in September 1998, halting its home computer business and cancelling both further development of RISC OS and the machine that was to succeed the Risc PC; Acorn Computers Limited was renamed Element 14 in January 1999 and the group was dismantled shortly afterwards, its residual shareholding in ARM being worth considerably more than the rest of it. comp.sys.arm outlived, by more than two decades, the company whose name sat next to it in the group list.

1990: Advanced RISC Machines, and the decision not to make chips

The company was incorporated on 12 November 1990 under the name Widelogic Limited and renamed Advanced RISC Machines Limited on 3 December, structured as a joint venture between Acorn Computers, Apple and VLSI Technology. Acorn contributed the design team — twelve employees — and VLSI contributed tools; Apple contributed money. The name changed from Acorn RISC Machine to Advanced RISC Machines at Apple’s request, according to Furber, on the reasonable ground that a company does not care to have a competitor’s name in its own.

The investment figure should be attributed rather than asserted. Reporting the deal on 28 November 1990, the Los Angeles Times wrote that Apple “has invested about $3 million (roughly 1.5 million pounds) for a 30% interest in the company, dubbed Advanced Risc Machines Ltd.” Later accounts give the same three million dollars and describe the three-way contribution in the same terms, but do not consistently repeat the shareholding; the contemporary newspaper figure is the one that can be dated. Larry Tesler, then a vice-president at Apple, was closely involved and helped recruit Robin Saxby as the joint venture’s first chief executive.

The commercial decision that followed mattered more than the money. Advanced RISC Machines did not build a fabrication plant and did not sell finished silicon. Its licensing terms varied in cost and in deliverable, but every licensee received an integratable hardware description of the core, a software development toolset and the right to sell manufactured chips containing it; integrated device manufacturers could take the core as synthesisable register-transfer-level source and optimise or extend it themselves. A semiconductor company could therefore put an ARM core into its own part without becoming an ARM customer in the ordinary sense, and its competitors could do the same. Nothing about the technology required this; a great deal about the group’s eventual character followed from it.

The company’s first profitable year was 1993. Silicon Valley and Tokyo offices opened in 1994. It floated on the London Stock Exchange and Nasdaq in 1998, changing its name in the process to ARM Holdings, and by February 1999 Apple’s stake had fallen to 14.8 per cent. Acorn’s remaining shareholding, about 24 per cent of the company, was worth some £300 million by the time Acorn was wound up — a subsidiary that had outgrown the parent so comprehensively that disposing of the holding became the main event of the parent’s dissolution.

What a room with this charter carried

No honest account can reconstruct particular conversations, and none is attempted here. But the charter is explicit about scope, and the architecture’s documented history says what was actually live in the years the group ran. A handful of recurring genres follow from both.

The address-space transition. ARM1 and ARM2 had a 32-bit internal structure but a 26-bit address space, capping addressable memory at 64 megabytes, with the processor flags packed into the top and bottom bits of the register that also held the program counter — a trick that let the whole machine state be saved in one operation on an interrupt. The address bus was extended to 32 bits with ARMv3 and the ARM6, but code compiled for the old model still had to live in the first 64 megabytes when the processor ran in 26-bit compatibility mode, and the compatibility mode is what kept the argument alive. In the RISC OS world it ran until well after the millennium: the first shipping 32-bit variant of the operating system, RISC OS 5, arrived on the Iyonix PC on 22 October 2002, and older software had to be rewritten, statically analysed for 26-bit-only instruction sequences, or emulated. That is a decade-long migration, conducted mostly in public, by people with working systems they did not wish to break.

Conditional execution and the barrel shifter. These are the architecture’s signature and the reason it reads unlike anything else in an assembler listing. Almost every ARM instruction carries a four-bit condition selector, so a short branch can be replaced by predicated instructions that simply do not take effect — useful on early parts that had no branch predictor at all. And a 32-bit barrel shifter sits in the data path, usable without a performance penalty on most arithmetic operations and address calculations, so that shifting and operating are one instruction rather than two. Both features cost encoding space — the predicate alone takes four of the thirty-two bits — and both were argued over on their merits for as long as the architecture was 32-bit.

The support chips, which the charter names. A charter that mentions memory and video controllers in its first sentence is describing a group where the processor was rarely the whole question. The 1988 posting is candid about what MEMC imposed: its inverted page table was a content-addressable memory of 128 entries, which gave “rather large pages (32KBytes with 4MBytes of RAM)” and made it impossible to have the same page at two virtual addresses. “Our UNIX hackers revolted,” the author notes, “but are now learning to love it.” The same chip drove DRAM page mode, helped by a prediction signal from the processor announcing that the next cycle would use a sequential address. Constraints of that kind are exactly what a board-level engineer needs to be told about, and exactly what does not appear in an instruction-set manual.

Floating point. For the first generation there was none in hardware. The 1988 posting describes a floating-point coprocessor interface chip working “in the lab” — the fifth member of a four-chip set — which bridged an AT&T WE32206 to the ARM coprocessor bus, and reports 95.5 KFLOPS on a LINPACK double-precision Fortran benchmark against 11 KFLOPS with the software emulator on the same machine. A ninefold gap between emulated and assisted floating point is the sort of number that decides what a piece of scientific code runs on, and the question of what to do about floating point stayed live across the architecture’s embedded decades.

The compressed instruction set. Thumb was introduced with the ARM7TDMI in 1994 — the T in the name — as a 16-bit encoding of a subset of the instruction set, entered as a separate processor state. Most Thumb instructions map onto ordinary ARM instructions; the saving comes from making operands implicit and restricting register access, and in Thumb only branches are conditional. On a device whose memory bus is narrower than 32 bits, the shorter encoding is faster as well as smaller, which is why the practice grew up of compiling for Thumb and hand-writing the hot loops in full ARM code. Thumb-2, introduced with the ARM1156 core announced in 2003, added 32-bit instructions back into the Thumb set and brought a unified assembly language with it.

The core families. ARM7 cores were released from 1993 to 2001, of which the ARM7TDMI and its synthesisable variant were much the most widely licensed; ARM9 and ARM11 followed, and the Cortex families after them. For an engineer, the practical consequence of the licensing model was that two chips from different vendors could share a core and behave differently in every respect around it, which is a fertile source of questions.

StrongARM and XScale. Digital Equipment Corporation licensed the ARMv4 architecture and, from 1995, built the StrongARM at a design centre in Palo Alto under Dan Dobberpuhl, aiming at the upper end of the low-power embedded market, at personal digital assistants and set-top boxes. The first part was the SA-110, announced on 5 February 1996 in 100, 160 and 200 MHz versions; through that year it was the highest-performing microprocessor available for portable devices, and faster parts later turned up on upgrade cards for Acorn’s Risc PC. DEC sold the line to Intel in 1997 as part of the settlement of a patent suit between the two companies, and Intel used it to replace its ailing i860 and i960 RISC processors before introducing its own ARMv5TE implementation, XScale, in 2000. Intel sold the XScale applications-processor family to Marvell in June 2006. Two of the most talked-about ARM implementations of the group’s active years, in other words, were made by companies that had arrived at the architecture from entirely different directions and left it again.

Endianness. ARM is little-endian by default and has been bi-endian from ARMv3 onwards, with a bit in the current program status register selecting data endianness. Anyone moving code or file formats between an ARM system and a big-endian host met this immediately, and the 1988 posting’s four-instruction byte-reversal sequence is a fair emblem of how often it came up.

Tools, ports and debug interfaces. Compilers, assemblers and the arguments about them are the permanent substrate of any architecture group. The 1988 posting already describes an ANSI C compiler with graph-colouring register allocation, code motion, dead-code and tail-call elimination, alongside Fortran 77, ISO Pascal, BBC BASIC, Forth, Algol, APL, Smalltalk-80, Lisp, Prolog, ML and BCPL; it also records VLSI porting the VRTX real-time executive, the Cambridge Computer Laboratory’s Tripos running on the A310 and A440, and Minix ports “everywhere one looks”. On the hardware side, the ARM7TDMI introduced JTAG-based on-chip debug, which the preceding ARM6 cores had not supported: the D in the name stands for a JTAG test access port for debugging and the I for an on-chip in-circuit emulation module supporting hardware breakpoints and watchpoints, and later cores kept and extended it. Board bring-up, boot loaders and the choice of a real-time operating system belong to the same conversation; for the RTOS side of it see comp.os.psos.

Out of the desktop

The architecture left the British desktop early and never came back to it in that form. Apple’s Newton MessagePad of 1993 used the ARM610; the 3DO Interactive Multiplayer, released in October of the same year, was built around a 12.5 MHz ARM60; the Nokia 6110, announced on 18 December 1997, was the first GSM telephone to use an ARM processor; the Game Boy Advance of 2001 ran an ARM7TDMI at about 16.8 MHz. Each of these was a licensee’s part in a licensee’s product, and each brought a fresh population of engineers to a group that had been founded largely by people with Acorn machines under their desks.

Claims about how far it went should be attributed to whoever counted. Arm itself announced on 27 February 2017 that its partners had cumulatively shipped 100 billion chips, and Simon Segars, then chief executive, put the figure at 200 billion in an Arm post of 18 October 2021. These are the designer’s own numbers for parts shipped by its licensees, not an independent audit, and they are the numbers the trade press generally repeats.

The ownership changes all postdate the 2000–2004 window this directory documents, and are noted here only so that a reader arriving from a course reading list is not left in 1998. SoftBank Group made an agreed offer for Arm on 18 July 2016 valuing the company at £24.3 billion, and the transaction completed on 5 September 2016. Nvidia announced on 13 September 2020 that it would buy Arm for a stated $40 billion in stock and cash; the deal met opposition on competition and national-security grounds and collapsed in February 2022. SoftBank then took Arm to the Nasdaq in 2023 at a valuation of $54.5 billion, retaining a large majority of the shares. Cambridge remains the headquarters throughout.

The group's own record today

The ISC newsgroups file still carries comp.sys.arm, and the description it carries is the line the 1994 Call for Votes specified: the charter line at the head of this page is that line, unaltered in more than thirty years. The active file lists the group as unmoderated, and lists the nine Acorn groups beside it with comp.sys.acorn.announce marked moderated. Both comp.sys.acorn and comp.sys.acorn.tech are absent, exactly as the February 1995 reorganisation decided.

The creation record in the news.announce.newgroups archive is complete: the Request for Discussion, the Call for Votes, and the result with the full list of voters. This is worth saying plainly because it is not always true — for many groups in this directory the paperwork is partial or gone. Here it is all present, which is why this page can date the group rather than estimate it.

The control-message archive holds one small oddity and one larger one. On 16 January 1995 a news server at a Tandem Computers site in Britain emitted two newgroup messages for comp.sys.arm within ten minutes of each other, carrying a different description, “Discussion of the arm architecture”; neither came from the Big-8 administrator, and messages of that kind used to leak out of misconfigured servers. The larger episode came on 31 August 1998, when a control message purporting to remove the group was posted from an address unconnected with news.announce.newgroups, cross-posted to news.groups, misc.test, alt.config, alt.test and a Microsoft support group, and asserting that comp.sys.arm “is widely considered a bogus newsgroup given that it passed its vote for removal by 233:30 as reported in news.announce.newgroups on 28 Aug 1998”. No such result exists in the news.announce.newgroups archive. The Big-8 group-admin address issued signed newgroup control messages for comp.sys.arm on 1 September 1998, twice, and again on 8 September, and the group is in the active file today. The control.ctl file distributed by ISC now instructs news servers to drop any newgroup or rmgroup for comp.* that is not cryptographically verified against the news.announce.newgroups key — a rule written precisely because of messages like that one.

Scope and limits

What can be established about comp.sys.arm is its charter, its creation, its neighbours and its administrative history, all from the Usenet administrative record, and the documented history of the architecture it existed to discuss, from published sources. What cannot be established is readership, volume, or the content of particular threads, and none of those has been guessed at here. The genres of traffic described above are inferred from the charter and from what was demonstrably live in the architecture at the time; they are not a summary of any archive.

Three factual disagreements have been left visible rather than smoothed over: the clock speed of ARM1, where the designer’s 1988 posting and the common secondary figure differ; the transistor count of the second-generation part, where the same posting and later reference works differ; and the size of Apple’s stake in the 1990 joint venture, where the contemporary press report and later accounts do not entirely line up. Where an investment figure, a price range or a shipment total appears above, the source that produced it is named.

Adjacent subjects have their own pages in this directory and are not retold here: the comp.* hierarchy, the Big-8 group-creation machinery at the soc.* hierarchy page, real-time operating systems for embedded work at comp.os.psos, and typesetting and the font question at comp.text.tex.